1. Field of the Invention
The present invention relates to a semiconductor memory device provided with a test circuit for implementing an operation test.
2. Description of the Prior Art
A conventional semiconductor memory device will be described by way of an example of a DRAM (Dynamic Random Access Memory) with a memory capacity of 4M bits.
FIG. 1 is a block diagram showing an example of 4-bit DRAMs. In the figure, a single input and output section 51 and two memory cell arrays 52a and 52b are allocated to each of four blocks 50. Further, in FIG. 1, the input and output section 51 for inputting a test signal and outputting a test result signal is shown at two different positions to facilitate understanding of the functions thereof.
Each of the memory cell arrays 52a and 52b can store information data of 512 kbits. Therefore, each block 50 has a memory capacity of 1M bits, and the device has a memory capacity of 4M bits in total.
To implement an operation test of the semiconductor memory device as described above, three switches 53a53b and 53c are first set to Test (T in FIG. 1) to input test signals through the input and output section 51, so that the same signal is written simultaneously in a single memory cell of the memory cell array 52a and a single memory cell of the memory cell array 52b. Therefore, when these two test signals are read simultaneously, an output of a logic circuit 57a (an inversion value of exclusive OR) is at a "high" level (referred to as H level, hereinafter), and an output of a logic circuit 57b (an non-inversion value of exclusive OR) is at a "low" level (referred to as L level, hereinafter), as far as the semiconductor memory device is operative normally. Accordingly, a MOS transistor 56a is turned on and a MOS transistor 56b is turned off, so that a signal of Vcc volt (the H level) is outputted from the input and output section 51. On the other hand, in case the semiconductor memory device is not operative normally, since the output signal of the input and output section 51 is at the L level, it is possible to discriminate the memory device as a defective device.
In the 4-bit DRAM as described above, since the memory cell array is divided into two in a single block 50, in the operation test the test signal is written in and read from the two memory cells simultaneously for each bit. Here, since the memory capacity of each memory cell array 52a or 52b is 512 kbits, the signal writing and reading operation is repeated 512.times.1024 times, in order to complete the overall operation test of a single DRAM.
FIG. 2 is a block diagram showing a similar example of 8-bit DRAMs with a memory capacity of 4M bits in total. In the DRAM shown in FIG. 2, a single memory cell array 62 is allocated to each of 8 blocks 60.
To implement an operation test, test signals are inputted to each memory cell array 62 with a memory capacity of 512 kbits through each of the 8 input and output sections 61, and then read therefrom. In this case, when the level of the read test signal is at "1", an output A is at an H level, and an output /A is at an L level, so that a MOS transistor 63a is turned on and a MOS transistor 63b is turned off in a read circuit 63. Therefore, a signal of Vcc volt (i.e., H level) is outputted from the input and output section 61. In contrast with this, when the signal read from the memory cell array 62 is at "0", a signal of 0 volt (i.e., L level) is outputted from the input and output section 61.
Further, a prior art 16-bit DRAM is almost the same as this 8-bit DRAM in device configuration. That is, the DRAM includes 16 blocks each having a single memory cell array and a single input and output section, without having any test circuit. Further, in the case of the memory capacity of 4M bits, the memory capacity of a single memory cell array is 256 kbits.
As described above, in the prior art multi-bit (8- or 16-bit) DRAM, being different from the case of the above-mentioned 4-bit DRAM, the test signal is written in and read from only a single memory cell simultaneously for each bit.
In the 8-bit DRAM shown in FIG. 2, since the memory capacity of the respective memory cell array 62 is 512 kbits, the signal writing and reading operation must be repeated 512.times. 1024 times in order to implement the overall operation test of a single DRAM.
Further, as already explained, in the case of the 16-bit DRAM whose memory cell capacity of a single memory cell array is 256 kbits, the signal writing and reading operation must be repeated 256.times.1024 times in order to implement the overall operation test of a single DRAM.
As described above, in the case of the multi-bit DRAMs of the same memory capacity, the repeated number of the test signal writing and reading operation required for the overall operation test of a single DRAM decreases with increasing number of bits.
In the actual operation test, however, since the number of the drivers and operators is limited, the number of chips which can be tested simultaneously by a single test system decreases, on the contrary, with increasing number of bits, with the result that it takes a long time to implement the operation test of the DRAMs.
The reason thereof will be described in more detail by taking the case of a test system whose number of drivers and comparators is 40, respectively and whose maximum number of simultaneous measurement is 8. That is, this test system is provided with 40 drivers for writing the test signals in the memory cells and 40 comparators for discriminating whether the read test signals are correct or not (in other words, 40 bits can be measured simultaneously), and further the maximum number of chips testable simultaneously is 8.
In the case of the operation test of the 4-bit DRAM, as shown in FIG. 3, the test system 71 can implement the operation test of 8 DRAMs 70 simultaneously (i.e., the same number as the maximum number of the simultaneous measurement). Further, in FIG. 3, P1 to P32 denote terminals (i.e., I/O pins) for connecting the input and output sections of the DRAMs to the test system 71, respectively.
Here, the test time T(4) required to implement the operation test of 100 units of 4-bit DRAMs 70 can be estimated by way of example as follows: ##EQU1## where k denotes a setup time required to implement a single operation test; and t denotes the time required to write and read a single test signal. Further, the signal writing and reading operation is repeated 512.times.1024 times for each operation test.
Here, if K=12.5 k, and T=12.5.times.2.sup.19 t, EQU T(4)=K+T
Further, as shown in FIG. 4, in the case of the operation test of the 8-bit DRAM 80, since the number of the drivers and the comparators is 40, the number of chips which can be tested simultaneously by the test system 71 is 5. Further, in FIG. 4, P1 to P40 denote the terminal for connecting the input and output sections of the DRAMs to the test system, respectively.
Here, the test time T(8) required to implement the operation test of 100 units of 8-bit DRAMs 80 can be estimated by way of example as follows: ##EQU2##
Accordingly, EQU T(8)=1.6 (K+T)
Further, in the case of the operation test of the 16-bit DRAMs (not shown), the number of chips which can be tested simultaneously is 2.
Here, the test time T(16) required to implement the operation test of 100 units of 16-bit DRAMs can be estimated as follows: ##EQU3##
Accordingly, EQU T(16)=4.0 (K+0.5 T)
That is, the test time of the 8-bit DRAMs 80 is about 1.6 times longer than that of the 4-bit DRAMs 70. Here, the time required to write and read data in and from a single cell is about 300 ns at the most; and on the other hand, several tens of seconds are required as the setup time when the ambient temperature is high, so that K&gt;&gt;T. Accordingly, the test time of the 16-bit DRAMs is about 4 times longer than that of the 4-bit DRAMs. In other words, the time required for the operation test increases with decreasing number of chips testable simultaneously.
In order to reduce the time required to implement the operation test of the multi-bit DRAMs, it may be possible to divide the memory cell array corresponding to a single bit into two or more arrays, in the same way as with the case of the above-mentioned 4-bit DRAM 70 shown in FIG. 1.
In the case of the multi-bit DRAMs, however, it is practically impossible to divide the memory cell array of a single block into two or more, because the chip size inevitably increases and therefore the cost thereof also increases.
In addition, since the K&gt;&gt;T as described above, even if the time t required for single test signal writing and reading operation is reduced, it is impossible to sufficiently reduce the total time required for the operation test.
Further, without being limited to only DRAMs, other semiconductor memory devices involve the same problem as described above.